PIN |
|
description |
CK, /CK |
DDR |
Differential System Clock |
CKE |
|
Clock enable |
/CS |
|
Chip Select (active low) |
/RAS |
|
Row Address Strobe (active low) |
/CAS |
|
Clolumn Address Strobe (active low) |
/WEd |
|
Write enable (active low) |
A0 ... A12 |
|
Address Input |
BA0 ... BA1 |
|
Bank Address Input |
DM0 ... DM3 |
|
Input Data Mask |
DQS0 ... DQS3 |
|
Data Strobe |
DQ0 ... DQ31 |
|
Data Input/Output |
Vdd |
|
Power Supply |
Vddq |
|
Data out Power |
Vss |
|
Ground |
Vssq |
|
DQ Ground |
/CE |
NAND |
Chip enable (active low) |
/RE |
|
Read enable (active low) |
/WP |
|
Write protection (active low) |
/WEn |
|
Write enable (active low) |
ALE |
|
Address Latch enable |
CLE |
|
Command Latch enable (command provided via IO0...IO7 and latched on
rising edge of /WE) |
R /B |
|
Ready/Busy output (chip busy writing when low, can be read when high) |
IO0 ... IO7 |
|
Data input/output |
Vcc |
|
+3.3V Power Supply |
Vss |
|
Ground |
NC |
- |
not connected |
DNU |
|
do not use |